This invention relates to a memory device and in particular to a charge storage structure built utilizing silicon-rich technology.
Floating gate storage FET devices are well known in the technology where a conductor, usually Si, is embedded in an insulator layer. Such memory elements store information and allow for information modification and erasure. Some floating gate devices have employed Si-rich layers as conductors for charge injection enhancement, but cannot store discrete charges in the Si-rich layers due to the presence of a conductive layer adjacent to the Si-rich region.
FET structure used for such memory elements is typified by U.S. Pat. No. 3,649,884 which utilizes a field effect transistor provided with a gate assembly. The gate assembly therein comprises a sandwich of a layer of SiO.sub.2 with excess Si disposed between two insulating films of appropriate thickness for the entrapment of charge carriers in the silicon-rich SiO.sub.2 layer. This triple layer is disposed between the gate electrode and the substrate. This device requires a thin, 30-40 .ANG., insulator on the bottom of the Si-rich layer otherwise tunneling cannot occur. However, charge leakage problems occur due to the thinness of the insulator.
Another example of an electrically alterable floating gate memory device is disclosed in U.s. Pat. No. 4,253,106. A silicon-rich oxide layer is disposed between the control gate and the floating gate.
A difficulty in prior art floating gate systems using embedded conductors is charge leakage if the structure is defective. Since the conductor can be considered an entity, charge tends to leak off eventually resulting in complete discharge and loss of the stored information. It is of course desired to have a memory device programmed to retain the information over an extended period of time until programmed without loss of charge.
Another of the difficulties of such electrically erasable programmable read only memory (EEPROM) devices is a need for significant amounts of chip real estate due to the floating gate structure.